A thrust of integrated circuit design has been the development of integrated circuits capable of higher frequency operation and/or lower power consumption. The ability of an integrated circuit to operate at high frequencies with low power consumption is generally determined by characteristics of active and passive elements in the integrated circuit, such as resistance and parasitic capacitance.
Referring to FIGS. 1A, 1B, and 1C, in order to reduce the drain and source resistances Rd, Rs of an NMOS transistor 10′ or a PMOS transistor 10″, silicide layers SA comprising a low-resistance metallic material and silicon are formed on surfaces of a polysilicon gate GP, a source S, and a drain D using a self-aligned silicidation (hereinafter “salicidation”) process. In applying the salicidation process, a discharge space for the transistor is defined at a region A at a junction disposed under a spacer GS adjacent the polysilicon gate GP. When electrical transients arising from electrostatic discharge (ESD) or electrical overstress (EOS) occur at a pad (not shown) connected to one of the source S or the drain D, the discharge space A may not be sufficiently large enough to prevent physical damage.
Input/output circuits are commonly designed to protect internal portions of an integrated circuit from transients arising from ESD, EOS, peak voltage, current surge, or noise. They also commonly provide voltage conversion between the voltage used by the internal portions and the voltage used by externally connected circuits, e.g., conversion of signals from CMOS to TTL or from TTL to CMOS. Input/output circuits also often include transistors with larger channel widths that can support higher currents which may arise from resistance, inductance, and capacitance of a printed circuit board (PCB) on which the integrated circuit is mounted and cables connecting the integrated circuit to external systems.
For example, a structure, as shown in FIG. 2A, that includes multiple transistors including a plurality of polysilicon gate layers 3 formed on a diffusion region 1 including source and drain regions S, D may be used. As can be seen in the cross-section in FIG. 2B, the substrate P-sub and the source and drain regions S, D form parasitic horizontal NPN bipolar transistors Q1, Q2 that provide a discharge path. Resistances between the bases of the parasitic transistors Q1, Q2 can prevent simultaneous turn-on of the transistors Q1, Q2. Therefore, it may take a significantly long time for all of the transistors Q1, Q2 to be turned on to provide a discharge path in response to an electrical transient. In the structure illustrated, the turn-on time of all the bipolar transistors Q1, Q2 is generally dependent upon values of on-resistance determined by dimensions of overlapped regions between the polysilicon gates 3 and the drains D. However, as described above, a relatively small on-resistance may be provided by a transistor fabricated by a salicidation process, which may provide insufficient RC delay time to enable a desired level of conduction of the transistors Q1, Q2. This can result in insufficient ESD protection.
A protection circuit, such as a diode or silicon-controlled rectifier (SCR), may be used to provide ESD protection for an output drive circuit that includes MOS transistors produced by a salicidation process. It is generally desirable to provide a protection circuit capable of driving a large current at a relative low voltage, as it is generally desirable that the protection circuit discharge excessive transients before the MOS transistors of the output drive circuit exhibit break down. However, it may be difficult to provide a protection circuit with high current capability at a relatively low turn-on voltage.
One way of dealing with this problem is to raise the turn-on voltage of the output drive circuit. For example, turn-on voltage may be raised by increasing a base width of a parasitic LNPN bipolar transistor associated with a MOS transistor of a drive circuit. However, increasing the base width of a parasitic LNPN associated with an output drive circuit MOS transistor can result in a need to increase circuit area to compensate for lower current drivability.
FIG. 3 illustrates another way to increase the turn-on voltage of an output circuit 100 including a PMOS transistor 101 and an NMOS transistor 102 that drive an external signal pad PAD and are protected by a protection circuit 20. As shown, turn-on voltage of the NMOS transistor 102 may be increased by placing a resistor Rs in series with the NMOS transistor 102. This can restrain activation of a parasitic LNPN, but, as with extending base width, can lead to increased circuit area to offset weak current drivability due to the additional resistor.
Another technique to protect a breakdown of an NMOS transistor by raising a turn-on voltage of an output circuit beyond that of a protection circuit is shown in FIGS. 4A-4F. In particular, a base width of a parasitic LNPN can be extended by connecting NMOS transistors of an output circuit 110 and a protection circuit 120 in series.
Two ways of connecting the transistors are shown in FIGS. 4B-4C and FIGS. 4D-4E, respectively. Referring to FIGS. 4B and 4C, active regions of two NMOS transistors N1 and N2 are separated, and a source of the NMOS transistor N1 is connected by a metal line M to a drain of the NMOS transistor N2, which is grounded. FIGS. 4D and 4E show a configuration where the source of the NMOS transistor N1 and the drain of the NMOS transistor N2 are connected through an active region, which can more efficiently use circuit area.
Although the configurations shown in FIGS. 4B-4E can extend a base width between a drain connected to a pad PAD (i.e., a collector of the parasitic LNPN) and a source connected to the ground voltage Vss (i.e., an emitter of the parasitic LNPN), these configurations may not provide a desirable current gain because of presence of a parasitic bipolar transistor Q3 having an extended base width (see FIG. 4F). This can lead to poor ESD protection.
Other techniques for improving ESD protection for a salicidation MOS transistor are shown FIGS. 5A, 5B, 6A and 6B. In FIG. 5A, after forming N+ source and drain regions S, D in a substrate P-sub by means of an ion implantation, a part of an insulation film 41 formed on top spaces of the polysilicon gate layer GP and source/drain regions is removed. An opening 42 is then formed, exposing parts of the gate layer GP and the source and drain regions S, D. After a local salicidation using the insulation film as a mask, silicide films 44 are formed on the exposed surfaces of the gate layer and the source/drain regions S, D as shown in FIG. 5B. The configuration shown in FIGS. 5A and 5B can provide base width extension, but may be difficult and/or expensive to manufacture and may not provide desirable high frequency operation due to increased parasitic resistance.
Referring to FIGS. 6A and 6B, an NMOS transistor is fabricated by forming source and drain regions S, D in a substrate P-sub forming extended diffusion regions S′ and D′ under the source and drain regions S and D by means of a high-energy ion implantation, and then performing a salicidation process. Although the double-diffused salicidation transistor shown in FIG. 6B may have a wider discharge space due to the use of the deep-extended diffusion regions S′ and D′, the transistor may exhibit increased resistance and may require additional process steps for its fabrication. In addition, such a transistor may not have desirable ESD protection.